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SM5M2
SM5M2
DESCRIPTION
The SM5M2 is a CMOS 4-bit single-chip microcomputer operated on 3.0 V single power supply. This microcomputer integrates 4-bit parallel processing function, ROM, RAM, display RAM, 15stage divider, 2-kind of interrupt and 4-level of subroutine stack. With a built-in LCD drive circuit for a maximum of 136 elements, a 2-mode standby function, voice synthesizer and a melody generator circuit in a single chip, the SM5M2 permits the design of system configuration with a minimum of peripheral components. It can be used in a variety of products from handheld equipment to electrical appliances, such as hand held games with voice, and also achieves low power consumption.
4-Bit Single-Chip Microcomputer (LCD Driver)
PIN CONNECTIONS
72-PIN QFP TOP VIEW
(NC) VOCS OSCOUT OSCIN VDSP H0 H1 H2 H3 GND S33 S32 S31 S30 S29 S28 S27 S26
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
INTA (NC) P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 T F VOICE VR VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
(NC) S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 (NC)
FEATURES
* ROM capacity : 3 072 x 8 bits (For main program) 64k x 5 bits (For voice) 256 x 6 bits (For melody) * RAM capacity : 130 x 4 bits (including 34 x 4 bits display RAM) * Instruction sets : 51 * Subroutine nesting : 4 levels * I/O port : Input 1 Output 6 Input/output 7 * Interrupts : Internal interrupt x 1 (divider overflow) External interrupt x 1 (INTA) * Built-in voice synthesizer circuit (APCM) : Number of phrases : 256 Voice ROM : 64 k x 5 bits Bit rate : 25/35 kbps Number of coded bit : 5 bits Sampling frequency : 5/7 kHz Generation period : 9.1 to 12.8 s * Built-in main clock oscillator for system clock * Built-in sub clock oscillator for real time clock
* Built-in 15 stages divider for real time clock * Built-in LCD driver : 136 segments, 1/2 bias, 1/4 duty cycle * Built-in melody generator circuit : Melody ROM : 256 steps Generating time (at 32.768 kHz) : 32 s (MAX.) * Instruction cycle time : 25.9 s (MIN.) (at 70 kHz 10%) 61 s (TYP.) (at 32.768 kHz) When using the clock with the system clock. * Standby function * Supply voltage : 2.4 to 3.3 V * Package : 72-pin QFP (QFP072-P-1010)
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
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GND1 VOA RESET VDD2 CK2 CK1 TOSC S0 S1 GND S2 S3 S4 S5 S6 S7 S8 S9
SM5M2
BLOCK DIAGRAM
VDSP VOA
BLEEDER
RAM ROM
3 072 x 8-bit
96 x 4-bit
RD RE RF ACC X C HC
H0 H1 H2 H3 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20
DISP RAM
34 x 4-bit
PC SR x 4
IFA OSC2 FOR LCD REAL TIME CLOCK OSC1 FOR VOICE SYSTEM CLOCK IFD
B SB
ALU LCD DRIVER
INTA OSCIN OSCOUT CK1 CK2 RESET
DIVIDER
INTERRUPT CONTROLLER
MELODY CONTROLLER MELODY ROM
6 x 256-STEP
OSC
VOICE ROM START ADDRESS
VOICE FLAG
HARDWARE RESET CIRCUIT
RC P33
VOICE ROM
5 x 64 k-STEP
T TOSC VOSC VDD GND
EXPANDER
5 to 8-bit
D/A CONVERTER
S33
P0
P1
P2
P00
P01
P02
P03
P10
P11
P12
P13
P20
P21
P22 VOICE
VR
F
Nomenclature
ACC : ALU : B : C : HC : IFA : IFD : RC : OSCIN,OSCOUT : Accumulator Arithmetic logic unit RAM address register Carry flag Common signal generator circuit External interrupt flag Divider overflow flag Voice starting address Oscillator for LCD and real time clock
P0-P2 : Port registers P33 : Voice flag port PC : Program counter RAM : Data memory RD, RE, RF : Mode registers ROM : Program memory SB : Stack B register SR : PC stack register X : X register CK1,CK2 : Oscillator for voice and system clock
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SM5M2
PIN DESCRIPTION
PIN NAME GND, VDD, VDSP, VR T, TOSC, VOSC I/O I I FUNCTION Power supply pins. The VDD, VDSP, VR pins apply a positive supply with respect to the GND. LSI chip test pins. Cannot be used by the user. Connect T and TOSC to GND. Connect VOSC to VDD. Input pin with built-in pull-up resistor. Hardware-reset the LSI chip when a Low RESET I level signal is input. Normally, a capacitor is connected between it and GND to form a power-on reset circuit. Crystal oscillator pins. Connect a crystal oscillator accross [OSCIN-OSCOUT ] to form a clock generator circuit. RC oscillator pins. Connect a resistor across [CK1-VDD ] to form a clock generator circuit. CK2 is used to test its clock out. Voice output pin. Output the contents of a voice ROM. Melody output pin. Outputs the contents of a melody ROM with standard 12 musical scales (555 to 2 114 Hz) in two octaves. Pins for the LCD's common signals. Pins for the LCD's segment signals. Input pin for external interrupt. The IFA flag is set at the rising edge of INTA. Output ports. The P0 ports are an output port. The accumulator ACC can be transferred to this port by instruction. P1 and P2 are I/O pins which can switch to input or output pins in 4/3-bit units by instruction. They can be used as output pins when configured for a key matrix. The SM5M2 is forced to hardware-reset when all of P10-P13 pins are High level. (By mask option)
OSCIN, OSCOUT CK1, CK2 Voice F H0-H3 S0-S33 INTA P00-P03
I/O I O O O O I O
P10-P13, P20-P22
I/O
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SM5M2
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply voltage Input voltage Output voltage SYMBOL VDD VI VO IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IOH IOL TOPR TSTG RATING -0.3 to 4.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 2 2 2 2 2 100 2 2 10 10 0 to 50 -55 to 150 UNIT V V V mA mA mA mA mA A mA mA mA mA C C 1 2 3 4 1 2 3 4 NOTE
Source output current for each pin
Sink output current for each pin
Total source output current Total sink output current Operating temperature Storage temperature
NOTES :
1. 2. 3. 4. Applicable Applicable Applicable Applicable pins pins pin pins : : : : P00-P03 P10-P13, P20-P22 F H0-H3, S0-S33
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply voltage Instruction cycle Oscillation starting voltage SYMBOL VDD TSYS VOSC RATING 2.4 to 3.3 Crystal+CR 25.9 to 31.7 Crystal 61.0 2.0 UNIT V s V 1 NOTE
NOTE :
1. Use the crystal oscillation circuit
Oscillation Circuit
* Crystal oscillation (frequency = 32.768 kHz)
OSCIN OSCOUT CK1 CK2
* CR oscillation (frequency = 70 kHz)
OSCIN OSCOUT CK1 R CK2 VDD
Crystal C1 C2
Crystal : 32.768 kHz C1 = 15 pF C2 = 15 pF
Crystal C1 C2
Degree of fluctuation frequency : 10% (VDD = 3 V, TOPR = 25C) C1 = 15 pF, C2 = 15 pF, R = 1.0 M
NOTE : In case of using RC resonator, crystal is also required.
NOTE : Mount the R, C and crystal as close to the LSI chip as possible to minimize the effects of stray capacitance.
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SM5M2
DC CHARACTERISTICS
PARAMETER SYMBOL VIH1 Input voltage VIL1 VIH2 VIL2 IIH1 IIH2 IIL1 -IOH1 IOL1 -IOH2 Output current IOL2 IO1 IO2 IO3 IOP11 IOP12 ISt11 ISt12 ISt13 Supply current IOP21 IOP22 ISt 21 ISt 22 ISt 23 ISt 24 DCOM DS CONDITIONS MIN. 0.8 x VDD 0 VDD -0.25 0 VIH = VDD VIH = VDD VIL = 0 V VOH = VDD - 0.5 V VOL = 0.5 V VOH = VDD - 0.5 V VOL = 0.5 V D = 1FH D = 0FH D = 01H CRRUN1 CRRUN2 CRSTOP1 CRSTOP2 CRSTOP3 XTALRUN1 XTALRUN2 XTALHALT1 XTALHALT2 XTALHALT3 XTALSTOP VDD=3.0 V VDD=3.0 V 500 1 000 500 25
(VDD = 2.4 to 3.3 V, TOPR = 0 to +50C)
TYP. MAX. VDD 0.2 x VDD VDD 0.25 30.0 30.0 25.0 1 300 2 000 1 300 90.0 980 740 200 120 110 15.0 4.00 3.00 50.0 40.0 30.0 26.0 26.0 4.0 15 30
10. Applicable pins : H0-H3 11. Applicable pins : S0-S33
UNIT V V
NOTE 1 2 3
Input current
A
4 5 6 7
A
8 150 130 40.0 15.0 13.0 100.0 80.0 60.0 52.0 52.0 15.0 k 10 11 A 9
Output impedance
NOTES :
1. Applicable pins : P10-P13, P20-P22 2. Applicable pins : OSCIN, RESET, T, INTA 3. Applicable pins : P20-P22 4. Applicable pins : P10-P13 5. Applicable pin : RESET 6. Applicable pins : P00-P03, F 7. Applicable pins : P10-P13, P20-P22 8. Applicable pins : VOICE, value of external resistor = 2 k 9. Measurement conditions in detail are mentioned in the tables next page.
VDD VOA GND
LCD wave form (EXAMPLE)
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SM5M2
CR + X'TAL Standby Mode STATUS CRRUN1 CRRUN2 CRSTOP1 CRSTOP2 CRSTOP3 STOP 0 0 1 1 1 P33 1 0 0 0 0 RF1 1 1 1 0 0 RD2 0 0 0 0 1 CR ON ON OFF OFF OFF X'TAL ON ON ON ON ON CPU ON ON OFF OFF OFF Voice ON OFF OFF OFF OFF LCD ON ON ON OFF OFF Divider ON ON ON ON OFF
NOTES :
* When CR = OFF, CPU and Voice are OFF. * When Divider = OFF, neither LCD nor Melody is in operation (undefined). * STOP = 1 stands for executing STOP instruction.
Only X'TAL Standby Mode STATUS XTALRUN1 XTALRUN2 XTALHALT1 XTALHALT2 XTALHALT3 XTALSTOP STOP 0 0 0 0 0 1 HALT 0 0 1 1 1 0 P33 1 0 0 0 0 0 RF1 1 1 1 0 0 0 RD2 0 0 0 0 1 0 CR OFF OFF OFF OFF OFF OFF X'TAL ON ON ON ON ON OFF CPU ON ON OFF OFF OFF OFF Voice ON OFF OFF OFF OFF OFF LCD ON ON ON OFF OFF OFF Divider ON ON ON ON OFF OFF
NOTES :
* * * * When CR = OFF, CPU and Voice are OFF. When Divider = OFF, neither LCD nor Melody is in operation (undefined). STOP = 1 stands for executing STOP instruction. HALT = 1 stands for executing HALT instruction.
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SM5M2
SYSTEM CONFIGURATION A Resister and X Register
The A register (or accumulator : ACC) is a 4-bit general purpose register. The register is mainly used in conjunction with the ALU, C flag and RAM to transfer numerical value and data to perform various operations. The A register is also used to transfer data between input and output pins. The X register (or auxiliary accumulator) is a 4-bit register and can be used as a temporary register. It loads contents of the A register or its content is transferred to the A register. When the table reference instruction PAT is used, the X and A registers load ROM data. A pair of A and X registers can accommodate 8-bit data.
3 0
The ALU operates binary addition in conjunction with RAM, C flag and A register. The carry signal Cy is generated if a carry occurs during ALU operation. Some instructions use Cy : ADC instruction sets/clears the content of the C flag; ADX instruction causes the program to skip the next instruction. Note that Cy is the symbol for carry signal and not for C flag.
B Register and SB Register
* B register (BM, BL) The B register is an 8-bit register that is used to specify the RAM address. The upper 4-bit section is called BM register and lower 4-bit BL. * SB register The SB register is an 8-bit register used as the save register for the B register. The contents of B register and SB register can be exchanged through EX instruction.
3 0 3 0
A register EXAX instruction
3 0
X register
Fig. 1 Data Transfer Example Between A Register and X Register
B register
BM register
BL register EX instruction (swap)
Arithmetic and Logic Unit (ALU) and Carry Signal Cy
The ALU performs 4-bit parallel operation.
4-bit data 4-bit data
7
0
SB register
Fig. 3 B Register and SB Register
ALU
Result of operation
Areg
c
Fig. 2 ALU
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SM5M2
Data Memory (RAM)
The data memory (RAM) is used for data storage. The RAM capacity consists of 130 x 4-bit (include 34 x 4-bit display RAM). Display RAM, which outputs data to an external pin for driving the segments of the LCD. Therefore, by writing data to the display RAM, the LCD can be driven at 1/4 duty (1/2 bias) to enable automatic display of the LCD. As shown in Fig. 5 the display RAM is connected to segment outputs port from S0 to S33 which correspond to the LCD common outputs H0 to H3. Data M0 to M3 for one column of the display RAM is output pins as a LCD drive waveform which corresponds to outputs H0 to H3. As a RAM, the display RAM operates exactly the same as other RAMs.
BM
BL
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0 1 2 3 4 5 8 9 A B S0 S1 S32 S33 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31
The area surrounded by the thick line represents the display RAM where S0 to S33 corresponds to the segment output.
Fig. 4 RAM Organization
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SM5M2
Common outputs (Register) BM = 1000 BL = 0000 BM = 1001 BL = 0000 BM = 1000 BL = 0001
H3
H2
H1
H0
Segment
S0 S1 S2
BM Register BM = 1000
LCD drive circuit
BM = 1001 BL = 1111 BM = 1010 BL = 0000 BM = 1011 BL = 0000
S31 S32 S33
M3 M2 M1 M0 (RAM bit)
Fig. 5 Relationship between The Display RAM and LCD Segment Outputs/Common Outputs
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SM5M2
Program Counter PC and Stack Register SR
A ROM address is specified by the program counter (PC). The PC comprises 12-bit where 6bit (PU) are used to specify the page (see Fig. 6) and 6-bit (PL) are used to specify the step. PU is a register and PL is a binary counter. The table reference instruction PAT executes a similar operation to that of the subroutine jump and uses one level of the stack register.
Program counter PC
Page Step
PU
MSB
PL
LSB
Push SR ( level 1 ) SR ( level 2 ) SR ( level 3 ) SR ( level 4 )
Stack register SR
Pop
Program Memory (ROM)
The ROM is used for program storage. The ROM capacity of the SM5M2 is 3 072-step . The ROM is organized into 48-page where one page is organized into 64-step.
Fig. 6 Program Counter PC and Stack Register SR
Page 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH PU 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111
Program First page Interrupt Standby Table start of release reference subroutine page PAT TRS
Page 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH PU 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111
Page 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH PU 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111
Last page
Fig. 7 ROM Organization
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SM5M2
Flags
The SM5M2 provides 4-flag (C flag and interrupt request flag ) which can be used to set or determine conditions.
SM5M2
INTA pin Level To ACC To interrupt controller
Output Latch Registers and Mode Registers
The output latch registers are connected to the P0, P1 and P2 pins. By instruction, the contents of the ACC can be transferred to the output latch registers. The SM5M2 also contains mode registers RC, RD, RE and RF. Setting the value of each register enables the voice start address, divider, LCD, melody or interrupt to be controlled. Setting a register is performed in the same way as the other output pins. The functions of the mode registers are shown in Table 1. * INTA pin INTA level can be loaded to ACC (bit 0), as follows. LBLX 4 IN INTA level does not through the noise debounce circuit.
Noise debounce circuit
CAUTION :
Connecting considerations of I/O port When using an I/O port as bidirectional bus such as data bus, avoid setting the I/O port to output when the target pin is also set output. Whenever the both output data conflict each other, system failure will be caused due to damaged circuits or instantaneous supply voltage drop.
SM5M2
DON'T
Data bus of the connected device
Output pin or I/O pin set output
Output pin
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SM5M2
Table 1 Mode Register Setting REGISTER TYPE RC BIT RC0 RC7 RD0 RD1 RD RD2 RD3 RE0 RE RE1 RE2 RE3 RF0 RF1 RF RF2 1 RF3 - 0 1 0 1 0 1 - 0 1 - 0 1 0 1 0 - SET VALUE - 0 1 MODE DESCRIPTION Sets voice synthesizer starting address. Clears the ME F/F to stop a melody. Sets the ME F/F to start a melody from a ROM pointer address. Sets by stop instruction (of melody code) and reset by TPB instruction. Accepts divider clock-in. Masks divider clock-in. Sets voice synthesizer to 7 kHz sampling rate. Sets voice synthesizer to 5 kHz sampling rate. Masks the interrupt based on the IFA flag. Accepts the interrupt based on the IFA flag. Sets "0" only. Masks the interrupt based on the IFD flag. Accepts the interrupt based on the IFD flag. No setting. Turns off the LCD. Turns on the LCD. Stops the function of a bleeder circuit. Operates the function of a bleeder circuit. Creates the system clock frequency by dividing two the main oscillation frequency. Creates the system clock frequency by dividing four the main oscillation frequency. Sets "0" only.
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SM5M2
System Clock Generator and Dividers
The main oscillation frequency (CR oscillator) which is input through CK1 is divided into 2 or 4 to generate the system clock fSYS (Fig. 8). System clock fSYS determines the execution instruction cycle so that the system clock period is the same as the instruction cycle. However, the instruction execution cycle of twoword instruction is twice that of one-word instructions.
OSCIN
Use of a CR oscillating element or a crystal oscillating element for the oscillator circuit is determined by the mask option. The crystal oscillator which is input through "OSCIN-OSCOUT" can be used as both real time clock and display signal of LCD. On the final stage of the divider, fc can be set 1 Hz or 2 Hz ( in case of 32 kHz crystal oscillation) depending on the mask option.
Divider
OSCOUT
OSC
OSCIN-OSCOUT : Crystal oscillation (32.768 kHz)
f14
111 222 1 2 111 222 1111111 2222222
f0
1 2
1 Hz
fC
4 kHz 2 kHz 256 Hz 2 Hz fC = 1 Hz or 2 Hz Determined by mask option
CK2
CK1
OSC
CK1-CK2 : CR oscillation (70 kHz)
1 2
1 2
fSYS MPX. fSYS = 17.5 kHz or 35 kHz
CG
RF2
Fig. 8 System Clock Generator and Divider
Either of the system clock frequencies 35 kHz or 17.5 kHz ( in case of CR oscillation) can be selected by the RF2 flag (See Table 2). The 17.5 kHz clock has slower command execution speed, but uses less power for the same function.
The system clock is initialized to 35 kHz after hardware reset operation. The Table 2 shows the relationship between the contents of RF2 flag for OSC resonator and the generated frequency, fSYS.
Table 2 OSC Resonator and Frequency fSYS FOR OSC RESONATOR 70 kHz CR oscillation 32.768 kHz crystal CONTENTS OF RF2 FLAG 0 1 0 1 GENERATED FREQUENCY fSYS 35 kHz 17.5 kHz 16.384 kHz 8.192 kHz
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SM5M2
FUNCTIONAL DESCRIPTION Voice Synthesizer
* How to select a voice start address There is a voice start address and RC, composed of 8-bit to select a voice start address. Voice start address is 16 bits. However, RC register can points only upper 8 bits in voice start address in partial. Lower 8-bit is always fixed "0". Refer to "RC register". Minimum unit (shortest block) is equal voice ROM capacity. Each minimum unit is composed of 256 steps. Refer to Fig.9. Core CPU detects the status whether voice synthesizer run or not, by reading the content of P33 flag. (P33 flag is "1" during voice generation.) Terminator (11111B) can be set as a voice data in the voice ROM. When controller found a terminator, immediately stops voice and reset a flag. When reached the bottom of the voice data address, voice data address automatically becomes 0000H and voice continuously generates until come across a terminator. CPU can reset the P33 flag and stop voice generation by force.
NOTE :
Voice ROM data "11111" means terminator of voice data. That is, an encoder must encode voice data except "11111".
NOTE :
A voice start address is corresponding to the RC register (8 bits). Maximum 256 (SM5M2) pieces of voice start address can be selected. Each voice start address is based on multiple number of 100H. When voice generates, P33 flag becomes "1".
* Voice start address
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 xxxxxxxx00000000
NOTE : "x" stands for "0" or "1"
Voice flag
7 0
Start address
Voice start address 0000H 0100H 0200H 0300H 0400H 0500H 0600H 0700H
Voice data (Voice ROM)
64k x 5 bits
7
0
RC register (8 bits)
3
0
3
0
FF00H
X register
Acc
Fig. 9 Voice ROM Configuration
* Voice sampling frequency (5 kHz / 7 kHz) In case of sampling frequency is 5 kHz, total generation period becomes 12.8 s. In case of 7 kHz, it's 9.1 s. Voice sampling frequency (5 kHz or 7 kHz) is selected by RD3 register. In case of RD3 is "0", voice sampling frequency becomes 7 kHz. In case of RD3 is "1", it's 5 kHz. * RC register The RC register is composed of 8-bit. It can points only upper 8 bits in the voice start address as shown below. The data is filled with both A and X registers.
First set the sampling rate of the voice synthesizer. The voice synthesizer start address is corresponding to the RC register and the 8 bits in the RC register are obtained by A and X register. After setting the P33 voice flag High, the voice synthesizer would start playing. After detect P33 Low, the voice synthesizer could play the next section of voice.
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SM5M2
Melody Output Function
The built-in melody generation circuit provides a variety of sound signals. Fig. 10 shows the block diagram of the melody generating circuit. The melody ROM can store notes, rest and stop commands in 256-step (1 step consists of 6-bit), allowing the generation of 12-scale over two octaves (555 to 2 097 Hz) and the section of the time base for notes (125/62.5 ms).
Melody ROM address set
16 Hz
8-bit preset binary counter (Melody ROM address pointer)
f8 (128 Hz)
1/2 1/2 1/2 1/2 RRRR
8 Hz Melody ROM 256-step x 6-bit
Preset signal
Time base select signal
Rest tell signal
Decoder
RD1 flag
RD0 flag
Melody start/stop flag
N-stage counter
32.768 kHz
RD0 flag : Bit 0 of RD register RD1 flag : Bit 1 of RD register Fig. 10 Melody Generating Circuit
F pin
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SM5M2
CONTROL PROCEDURE The binary counter for designating the address of the melody ROM can be arbitrarily set using the PRE instruction. A performance is started and stopped by the RD0-flag to "1" and "0". The stop code generates a "rest tell signal", and at the same time, sets the RD1 flag. The end of the melody can be found by testing the RD1 flag. Accordingly, to stop a performance at the end of melody, the RD0 flag must be clear upon detection of RD1 flag = 1. Next step of PRE instruction, put the NOP instruction. The following is an example of a melody generating program.
MELO LAX ATX LAX PRE 2 1 ; Set the starting address of the melody at the 21st. Hexadecimal step. ; Dummy command
: LBLX LAX OUT TPB NOP : : LBLX TPB TR LAX OUT
0DH 1 1 ; Start the melody ; Executed for clear the RD1 flag ; Dummy command
L1
0DH 1 L1 0
; Test the RD1 flag ; Loop for detect the stop code ; Stop the melody
Using these functions, the user can generate music, sound effects, alarm signals, etc. as desired, and any portion of the music can be repeated. Table 3 lists the melody output frequencies. The output frequency can be halved by making bit 5 (OCT) of the melody ROM Low (0). In Table 3, m0 to m3 show data in bits 1 to 4 of the melody ROM.
NOP :
Table 3 Melody Output Frequency m3 m2 m1 m0 do si la# la sol# sol fa# fa mi re# re do# 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 OUTPUT FREQUENCY (Hz) CLOCK NUMBER 1 2114.1 1985.9 1872.4 1771.2 1680.4 1560.4 1489.5 1394.4 1310.7 1236.5 1170.3 1110.8 15.5 16.5 17.5 18.5 19.5 21.0 22.0 23.5 25.0 26.5 28.0 29.5
7 8 8 9 9 10 11 11 12 13 14 14 8 8 9 9 10 11 11 12 13 13 14 15
2
8 8 9 9 10 10 11 12 12 13 14 15
8 9 9 10 10 11 11 12 13 14 14 15
1 Number of clocks for one cycle 2 The number (n) in the waveforms represents the number of periods of the oscillation frequency (32.768 kHz) from the crystal oscillator for the duration in that particular part of the waveform.
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SM5M2
MELODY ROM INSTRUCTION The melody ROM instruction is composed of 6-bit. This 6-bit instruction (1 set), corresponding to a musical note, generates a sound signal. EXAMPLE OF WRITING ON THE MELODY ROM An example of writing a tone such as the following, on the melody ROM will be shown.
l
OCT
m3
m2
m1
m0
MUSICAL SCALE TONE LENGTH (ms) OCT sol 375 0 0 la 125 0 sol 250 0 mi 250 1 do 375 1 re 125 1 do 250 0 la 250 m3 0 0 0 1 0 1 0 0 m2 1 1 1 0 0 1 0 1 m1 1 0 1 1 1 0 1 0 m0 1 1 1 0 0 0 0 1
l OCT
m3 - m0
: Control the tone length. When "1", 125 ms; when "0", 62.5 ms. : When the octave is "1", the frequency is determined by m3 -m0. When the octave is "0", 1/2 of the frequency determined by m3-m0. : Frequency as shown in Table 3. Pause when m3 = m2 = m1 = m0 = 0, stop instruction when m3 = m2 = m1 = 0, m0 = 1.
ADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11
DATA 00 27 27 27 25 27 27 2A 2A 22 22 22 3C 22 22 25 25 01
MUSICAL NOTE INSTRUCTION pause sol sol sol la sol sol mi mi do do do re do do la la stop
The tone length of an initial musical note which is generated from ROM addressed data assigned by a PRE instruction has an error of maximum 4 ms. Therefore, by applying a pause as an initial note, a melody performs with a precisely regulated tone length.
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SM5M2
Standby Function
A standby function is available which temporarily stops program execution to conserve power consumption. The state during which a program is in execution is called the operation mode and the state during which the execution is temporarily stopped is called the standby mode. Either CR or X' TAL oscillator can be selected to a system clock generator circuit of SM5M2. Each standby mode between CR + X' TAL and only X' TAL is entirely different as tables shown below. In case of CR + X'TAL oscillator, HALT instruction can NOT be used, only STOP instruction is available. On the other hand, in case of only X' TAL oscillator, both HALT and STOP instruction are available.
Table 4 CR + X'TAL Standby Mode Standby mode STATUS CRSTOP1 CRSTOP2 CRSTOP3 STOP 1 1 1 HALT 0 0 0 Register status P33 RF1 1 0 0 RD2 0 0 1 CR OFF OFF OFF X'TAL ON ON ON Chip's status CPU OFF OFF OFF Voice OFF OFF OFF LCD ON OFF OFF Divider ON ON OFF
NOTES :
* When CR = OFF, CPU and Voice are OFF. * When Divider = OFF, neither LCD nor Melody is in operation (undefined). * STOP = 1 stands for executing STOP instruction.
Table 5 Only X'TAL Standby Mode Standby mode STATUS XTALHALT1 XTALHALT2 XTALHALT3 XTALSTOP STOP 0 0 0 1 HALT 1 1 1 0 0 0 0 0 Register status P33 RF1 1 0 0 0 RD2 0 0 1 0 CR OFF OFF OFF OFF X'TAL ON ON ON OFF Chip's status CPU OFF OFF OFF OFF Voice OFF OFF OFF OFF LCD ON OFF OFF OFF Divider ON ON OFF OFF
NOTES :
* * * * When CR = OFF, CPU and Voice are OFF. When Divider = OFF, neither LCD nor Melody is in operation (undefined). STOP = 1 stands for executing STOP instruction. HALT = 1 stands for executing HALT instruction.
To get a condition mentioned in the first to the sixth boxes from right hand side, one of STOP or HALT instruction must be executed under the condition mentioned in the fourth to the sixth boxes from left hand side. For instance, to get the status of XTALHALT1, of which contents are CR = OFF, X' TAL = ON, CPU = OFF, Voice = OFF, LCD = ON, and Divider = ON in the only
X' tal standby mode, HALT instruction must be executed under the condition of P33 = 0, RF1 = 1 and RD2 = 0. NOTE :
The halt mode stops only system clock generator circuit. This mode is used to activate the system immediately after a condition causes a release to the operation mode.
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SM5M2
During the standby mode, the contents of the RAM and stack RAM are retained. The contents of the flags, registers and output latches shown below are also retained.
FLAG IFA flag IFD flag IME flag C flag P33 flag REGISTER ACC X register BM, BL register SB register SP SR RC, RD, RE, RF OUTPUT LATCH REGISTER P0 register P1 register P2 register
A release from the standby mode to the operation mode is performed by a reset port input, an interrupt from the nonmaskable INTA, any port High in Port 1, and divider. A maskable interrupt request cannot become a factor in releasing back to the operation mode. The mask setting is performed with RE register. (see Table 1) CAUTION :
When all of P10 to P13 level are High, the SM5M2 is performed to release the standby mode and enter normally hardware reset operation. (Mask option)
RELEASE FROM THE STANDBY MODE TO THE OPERATION MODE Release based on an interrupt request from the INTA pin or divider overflow. However, the reset or any port High in Port 1 is limited to a nonmaskable interrupt request. The program restarts from step 0 on page 3. However, if the IME flag is set, the instruction at step 0 on page 3 is executed and a subroutine jump is performed to the interrupt processing routine specified on page 2 according to the type of interrupt. Even if Low level input on INTA pin is removed before 900 command cycles, the stop mode is released. However, the program will not jump to 20H page (interrupt process routine). Interrupt request flag IFA is not set : the program continues at step 0 of page 3.
Interrupts
Interrupts originate from an INTA input or divider overflow. The IFA and IFD flags become interrupt request flags. The interrupt block is composed of mask flags (RE0, RE2), the IME flag and interrupt processing circuit. As shown in Fig. 11, resetting a mask flag enables the interrupt request flag to be independently masked. Thus, the mask flags can be used in a program to establish the interrupt priority. The priority for interrupts generated simultaneously is shown in Table 6.
TRANSITION FROM THE OPERATION MODE TO THE STANDBY MODE The HALT instruction is executed to set the halt mode and the STOP instruction is executed to set the stop mode. Since the interrupt is used to release from the standby mode, the mode does not transfer to the standby mode if any of the following conditions are satisfied during execution of the STOP or HALT instruction. a) RE0 is set and the INTA level is High. b) RE2 is set and the IFD flag is set. If any of the conditions above is satisfied, the mode does not transfer to the standby mode even if the STOP or HALT instruction is executed and the instruction at the address following that of the STOP or HALT instruction is executed. Therefore, place the JUMP instruction which specifies step 0 on page 3 to the location at the address following that of the STOP or HALT instruction.
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SM5M2
Stack register Program counter Mask flags Interrupt request flags IFA
RE2 RE0
INT signal
Interrupt processing circuit
IME IFD
Interrupt enable flag
Fig. 11 Interrupt Block Table 6 Interrupt Event Summary INTERRUPT REQUEST (REQUEST FLAG) INTA input (IFA) Divider overflow (IFD) JUMP DESTINATION PAGE 2 2 STEP 0 4 PRIORITY ORDER 1 2 INTERRUPT ENABLE FLAG RE0 RE2
When the IME flag is set, the interrupt circuit activates according to the interrupt request and a subroutine jump is performed to the specified address. The jump destinations according to interrupt origin are shown in Table 6. When the IME flag is cleared, an interrupt is not accepted even if an interrupt request is generated. The interrupt timing is shown in Fig. 12 and Fig. 13. The timing chart shown in Fig. 12 shows the interrupt enable state when an interrupt request has been generated. In this case, the interrupt processing signal INT goes High, one instruction cycle after the interrupt request flag is set. When INT goes High, the contents of the program counter are pushed into the stack register and execution jumps to the specified address. At this time, the INT signal and the IME flag are cleared to establish the interrupt disable mode. The IME flag is set again when the RTNI instruction is executed
to establish the interrupt enable mode. The timing chart shown in Fig. 13 shows the state when interrupts are enabled while multiple interrupts are generated. In this case, a subroutine jump is performed according to the interrupt having the highest priority. When returning from the subroutine by executing the RTNI instruction, the instruction (two words are executed for a two-word instruction) at the location of return is executed and the interrupt for the next highest priority is accepted. If an interrupt request is generated during execution of a two-cycle instruction, the instruction is executed after which interrupt processing is performed. If consecutive LAX instructions are skipped or if the SKIP conditions are satisfied, the skip operation is terminated after which interrupt processing is performed.
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SM5M2
Instruction cycle
System clock
Interrupt request flag
INT signal Interrupt enable flag
Interrupt processing routine
RTNI instruction
Interrupt processing routine
Fig. 12 Interrupt Timing Chart
Instruction cycle
System clock Interrupt request flag
Interrupt request flag
INT signal
Interrupt enable flag
Interrupt processing routine
RTNI instruction
Interrupt processing routine
Fig. 13 Interrupt Timing Chart
NOTE :
Fig. 12 and Fig. 13 show the case where the interrupt request flags are not masked.
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SM5M2
Hardware Reset Function
The hardware reset function mode activated two instruction cycles after the falling edge from the RESET pin. When the RESET pin is changed from High to Low, the pulse which is input by the OSCIN pin is counted 215 times after which the reset mode clears and the program counter starts from address 0 on page 0. The initialized status of the system after reset is shown in Table 7. The following reset functions are available. * The I/O port is set as an input port and the mode register RC, RD, RE and RF are cleared. The output only port (P0) is cleared and output Low. * The interrupt request flags (IFA, IFD) and the interrupt enable flag (IME) are cleared and all interrupts become disabled. * The program counter start from step 0 on page 0. For activate reset function, when power is turned on, you must connect a capacitor (0.1 F, TYP.) across the RESET pin and GND.
Table 7 Reset Status FLAG OR REGISTER, X-REGISTER PC SP RAM ACC X-register P0-P2 output latch registers Divider IFA flag IFD flag IME flag P33 flag C flag BM, BL registers Register RC (bit 7-0) Register RD (bit 1) Register RD (bit 0) Register RD (bit 3) Register RD (bit 2) Register RE (bit 2, 1, 0) Register RF (bit 3, 2, 1, 0) 0 Level 1 Undefined Undefined Undefined 0 0 0 0 0 0 Undefined Undefined 0 Undefined 0 0 0 0 0 STATUS ( in reset mode and at program start)
NOTES : * Undefined flags and registers should be initialized by software. * When all of P1 pins (P10 to P13) level goes to High, the SM5M2 is performed to reset operation. (Mask option)
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SM5M2
LCD Function
* Display segment The SM5M2 contains a built-in circuit which directly drive a 1/4 duty, 1/2 bias LCD. A sample LCD pattern is shown in Fig. 14.
H0 H1 H2 H3
S33
S32
S31
S30
S29
S28
S2
S1
S0
Fig. 14 LCD Pattern
A segment of the LCD can be turned on or off by setting the corresponding bit in the display RAM (see Fig. 5) to "1" or "0". The displayed segments can assume any configuration containing up to a maximum of 136 segments. An example of a 7segment numeric display is shown in Fig. 15.
T VDD (3 V) H0 VOA (1.5 V) GND (0 V) VDD (3 V) H1 VOA (1.5 V) GND (0 V)
H0 H1 H2
H2
VDD (3 V) VOA (1.5 V) GND (0 V) VDD (3 V)
H3
H3
VM (1.5 V) GND (0 V)
S1
S0
S0
VDD (3 V) VOA (1.5 V) GND (0 V)
Fig. 15 Sample LCD Pattern for 7-Segment Numeric Display
* LCD drive waveforms The LCD drive waveforms for the LCD pattern of Fig. 15 displaying a "5" are shown in Fig. 16 (the segment output uses S0 and S1). For Fig. 16, 3 V is applied to the VDD pin, and 1.5 V is applied to the VOA pin.
VDD (3 V) S1 VOA (1.5 V) GND (0 V)
Fig. 16 LCD Drive Waveforms (frame frequency = 1/T = 64 Hz or 128 Hz)
Frame frequency is selectable by mask option.
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SM5M2
* VOA pin Bleeder resistors are built-in to drive the LCD at 1/2 bias. The bieeder resistors have the configuration shown in Fig. 17. When bit 1 of the RF registor is set and VDD is 3 V, VOA output 1.5 V. Normally, the VOA pin is used in its open state. To drive an LCD with a large display area, the leading edge of the LCD drive waveform can be improved by connecting capacitor across the VOA pin and VDD. The same effect can be obtained by connecting capacitor across the VOA pin and GND. When bit 1 of the RF register is set "0", VOA drop to GND level to reduce power consumption. At the same time, the H0-H3 and S0-S33 pin are GND level. * Booster circuit It is necessary to apply external capacitors between VDD pin and VOA pin. (see Fig. 18) * Blank display There are two way to blank the entire display to match the purpose. (a) Blanking the display for a short time. Set bit 0 of the RF register to "1" : Display Set bit 0 of the RF register to "0" : Blank state (b) Blanking the display for a long period mainy to reduce supply current. Set bit 0 and 1 of the RF register to "1" : Display Set bit 0 and 1 of the RF register to "0" : Blank state When bit 1 of the RF register is set "0", the voltage (VDD) applied to the bleeder resistors is turned off and common outputs and segment outputs are dropped to GND level so that the display blanks. By cutting off the bleeder supply, the current consumption can be greatly reduced. However, when the display is blanked using method (b), the response speed of the LCD returning to the display state drops slightly. The RF register is in the blank state after initialization (reset state) from hardware reset.
VDD R1 RF1
VDD
VOA R2 R1= R2
SM5M2
Fig. 17 Booster Circuit
VDD
SM5M2
VOA
Fig. 18 Externally Connected Capacitor Circuit
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SM5M2
INSTRUCTION SET Definition of Symbols
The following symbols are used in descriptions for the instructions. M : Contents of RAM at the address specified by the B register : Transfer direction : Logical OR : Logical AND : Logical XOR Ai : ith bit of the ACC Push : Content of the PC are decremented to the stack register. Pop : The decremented contents are transferred back to the PC. Pj : Pj register ( j = 3, 2, 1, 0) Rj : Rj register ( j = F, E, D) ROM ( ) : ROM contents for address within ( ) Cy : Carry of ALU (different from the C flag) * Each bit of a register can be represented. For example, the ith bit of X register and R(0) register are represented as Xi and R(0) i. ( i = 0, 1, 2, 3, ...) * Increment and decrement denote the binary addition of 1H and FH, respectively. * To skip a certain instruction means that the instruction is ignored and that no operation is performed until the execution transfers to the next instruction. In other words, the instruction is regarded as a NOP instruction. Therefore, one cycle is required to skip a one-word instruction and two cycles are required to skip a two-word instruction.
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SM5M2
Instruction Summary
MNEMONIC MACHINE CODE OPERATION MNEMONIC TAM TC TM x TABL TPB x TA TD MACHINE CODE 6F OPERATION ROM Address Control Instructions PL x ( I5-I0) TR x 80 to BF PU x ( I11-I6) E0 to EF TL xy PL y ( I5-I0) 00 to FF TRS x C0 to DF F0 to FF 00 to FF 7D 7E 7F Push, PU 01H PL x ( I4, I3, I2, I1, I0, 0) Push, PU x ( I11-I6) PL y ( I5-I0) Pop Pop, Skip the next step Pop, IME 1 SM x RM x SC RC IE ID INL OUTL ANP ORP IN OUT Test Instructions Skip if ACC = M Skip if C = 1 Skip if Mi = 1 ( i = 3 to 0) Skip if A = BL Skip if P (R) i = 1 ( i = I1, I0) Skip if IFA = 1, and ( IFA 0) Skip if IFD = 1, and ( IFD 0)
6E 48 to 4B 6B 4C to 4F 6C 69 02 44 to 47 40 to 43 61 60 63 62
CALL xy RTN RTNS RTNI LAX x LBMX x LBLX x LDA x EXC x
Bit Manipulation Instructions Mi 1 ( i = 3 to 0) Mi 0 ( i = 3 to 0) C1 C0 IME 1 IME 0
Data Transfer Instructions ACC x ( I3-I0) 10 to 1F 30 to 2F 20 to 2F 50 to 53 54 to 57 BM x ( I3-I0) BL x ( I3-I0) ACC M BMi BMi x ( I1, I0) ( i = 1, 0) M ACC BMi BMi x ( I1, I0) ( i = 1, 0) M ACC, BL BL+1 BMi BMi x ( I1, I0) ( i = 1, 0) Skip if Cy =1(BL = 0FH 0) M ACC, BL BL+0FH
I/O Control Instructions ACC P1i ( i = 3 to 0) 70 P0i ACC ( i = 3 to 0) 71 Pj Pj ACC ( j = 3 to 0) 72 73 74 75 Pj Pj ACC ( j = 3 to 0) ACC Pj ( j = 3, 2, 1) Pj ACC ( j = 3 to 0) Rj ACC ( j = F to D)
EXCI x
58 to 5B
EXCD x EXAX ATX EXBM EXBL EX
5C to 5F 64 65 66 67 68
BMi BMi x ( I1, I0) ( i = 1, 0) Skip if Cy =1(BL = 0 0FH) ACC X x ACC BM ACC BL ACC B SB PAT
Table Reference Instruction Push 6A 00 to FF PU (0, 4), PL (X1, X0, ACC) (X, ACC) I7-I0 Pop
Divider Instructions DR DTA 69 03 69 04 DIV ( f7-f0) Reset ACC Divider ( f3 to f0)
Arithmetic Instructions ADX x ADD ADC COMA INCB DECB 00 to 0F 7A 7B 79 78 7C ACC ACC+x ( I3-I0), Skip if Cy = 1 ACC ACC+M ACC ACC + M+C, C Cy Skip if Cy = 1 ACC ACC BL BL+1, Skip if BL = 0FH BL BL-1, Skip if BL = 0
PRE
Melody Control Instruction Melody ROM pointer preset 6D Melody ROM pointer X, A Special Instructions 76 77 00 Standby mode (STOP) Standby mode (HALT) No operation
STOP HALT NOP
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SM5M2
SYSTEM CONFIGURATION EXAMPLE
* Handheld LCD game
VDD
VR
Hello! UP DOWN
VDD
VDD
TIME START SELECT
F VDD VDD 3.0 V GND VOSC T TOSC VDD VOA
RESET
VOICE 4 P10-P13 P20-P22 INTA 3
SHOT CHARGE
Pause key Open 34
SM5M2
P00-P03 S0-S33 4 H0-H3
To LCD panel
CK1 VDD
CK2
OSCIN
OSCOUT
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SM5M2
72 QFP (QFP072-P-1010)
0.5TYP. 54 55
0.2 0.08 37
0.08 (1.0)
M
0.15 0.05
36
0.2 0.3
11.0 0.2 0.65 1.45
0.2
72 1 (1.0)
10.0 0.2 12.0 0.3
18 (1.0)
(1.0)
19
10.0 12.0
0.1 0.1
0.2
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Package base plane
0.1

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